The present invention generally relates to the memory organization in computer systems with a multi-channel architecture.
FIG. 1 shows a principal arrangement of a computer system 10 with a multi-channel architecture. The computer system 10 comprises a main computer 20 for controlling the computer system 10, a data storage 30, and a plurality of individual channels 40AA, . . . , 40ZZ. Each one of the plurality of individual channels 40AA, . . . , 40ZZ comprises an individual channel memory 50AA, . . . , 50ZZ, and is connected via a system bus 60 to a controller 70 for controlling the plurality of individual channels 40AA, . . . , 40ZZ. It is to be understood that the controller 70 can also be part of the main computer 20, however for the sake of a better understanding, is referred herein as an individual element.
The multi-channel architecture distinguishes from other computer architectures in that the architecture of the computer system 10 allows a functioning of each one of the plurality of individual channels 40AA, . . . , 40ZZ independent of the other channels 40AA, . . . , 40ZZ.
Each one of the plurality of individual channels 40AA, . . . , 40ZZ might comprise an individual processing unit and therefore represent an `intelligent` channel. The main computer 20 represents a `central intelligence` of the computer system 10 and may control the plurality of individual channels 40AA, . . . , 40ZZ to a certain extent by means of the controller 70.
The data storage 30 can be any storage as known in the art, however, in most cases represents a `central storage` of the computer system 10 and is therefore in general a slower but larger storage medium than the `decentralized` channel memories 50AA, . . . , 50ZZ. The data storage 30 normally is a disk storage, whereas the channel memories 50AA, . . . , 50ZZ might be silicon memories such as a RAM (random access memory), a DRAM (dynamic random access memory), or an SDRAM (synchronous dynamic random access memory).
It is also to be understood, that the computer system 10 may also comprise a plurality of individual channels without respective channel memories. However, since those channels make no contribution to the memory organization in the multi-channel architecture, they are disregarded herein for the sake of simplicity.
The plurality of individual channels 40AA, . . . , 40ZZ can be connected with inputs and/or outputs of other devices and provide data thereto and/or receive data therefrom. However, since those devices also make no contribution to the memory organization in the multi-channel architecture, they are accordingly disregarded herein for the sake of simplicity.
FIG. 2 shows a principal arrangement of another embodiment of the computer system 10 with a multi-channel architecture. The arrangement of FIG. 2 differs from the arrangement of FIG. 1 in that one or more of the plurality of individual channels 40AA, . . . , 40ZZ according to FIG. 1 might be physically arranged on one or more channel boards 100A, . . . , 100Z. In the example of FIG. 2, channel board 100A contains channels 40AA, . . . , 40AZ, and channel board 10OZ contains channels 40ZA, . . . , 40ZZ. It is clear that the actual arrangement of the channels 40AA, . . . , 40ZZ and channel boards 100A, . . . , 100Z depends on the actual application.
The channels 40AA, . . . , 40ZZ are connected within the respective channel boards 100A, . . . , 100Z via a respective channel board bus 110A, . . . , 100Z, which also provides a connection with the system bus 60. In the example of FIG. 2, the channels 40AA, . . . , 40AZ are connected within the channel board 100A and to the system bus 60 via channel board bus 110A, and the channels 40ZA, . . . , 40ZZ are connected within the channel board 100Z and to the system bus 60 via channel board bus 110Z.
The system bus 60 and the channel board busses 110A, . . . , 110Z are generally embodied as relatively high speed busses, especially in comparison to the connection between the main computer 20 and the controller 70. The system bus 60 and the channel board busses 110A, . . . , 110Z can be physically and electrically separated by suitable means as known in the art, and are generally controlled by the controller 70.
An important application of the multi-channel architecture is in testing applications, e.g. for testing integrated circuits (IC's) or other electronic devices, such as the Hewlett-Packard HP 83000 Digital IC Test Systems. A typical testing unit comprises a tester circuit and a device under test (DUT), which can be an IC or any other electronic device. The tester circuit generally comprises a signal generating unit for generating and applying a stream of stimulus data to the DUT, a signal receiving unit for receiving a response on the stream of stimulus data from the DUT, and a signal analyzing unit for comparing the response with an expected data stream. Test data applied to the DUT is also called vector data or test vector and comprises one or more single individual vectors. Each individual vector may represent a signal state which is either to be applied at one or more inputs of the DUT or output by the DUT, at a given point in time.
A specific tester architecture following the multi-channel architecture of FIG. 1 is the so-called tester-per-pin or test-processor-per-pin architecture, wherein one of the plurality of individual channels 40AA, . . . , 40ZZ is provided for each testable pin of the DUT. The tester-per-pin architecture can be applied in a mono-site architecture, wherein only one DUT can be tested at once, or in a multi-site architecture, wherein a plurality of DUTs can be tested simultaneously and in parallel.
There are several testing methods known in the art to apply test data to the DUT. In a so called `parallel test`, the DUT input signal is applied at the inputs of the DUT and the outputs thereof are observed. During a SCAN test, states internal of the DUT can be sequentially changed and/or monitored directly. DUTs that allow SCAN test normally need special storage devices which can be written or read in a serial fashion. Boundary SCAN test is often used during a board test to directly change and monitor certain states at the boundaries of the DUTs on a board.
In certain applications of the computer system 10, such as testing applications, it might be required that one or more channels of the plurality of individual channels 40AA, . . . , 40ZZ provide a data stream, e.g. of sequential data, which should be preferably without interrupts. In that case, the respective one(s) of the channel memories 50AA, . . . , 50ZZ are loaded, e.g. sequentially, with a certain amount of data, which then again is output by the respective channel, e.g. to the DUT. It is apparent, that each (re-)loading of the channel memories 50AA, . . . , 50ZZ represents an interruption of the data stream which can be applied from one channel. However, it is also clear that a continuous loading or re-loading of data from the data storage 30 to the channel memories 50AA, . . . , 50ZZ of the individual channels 40AA, . . . , 40ZZ is generally impossible due to a different access speed to the data storage 30 and to the channel memories 50AA, . . . , 50ZZ. Further more, the connection between the main computer 20 and the controller 70 might also represent a `bottle-neck` in the data transfer from the data storage 30 to the channel memories 50AA, . . . , 50ZZ.
In other applications, it might (further) be required that the system bus 60 is used--to a certain period in time--only either for writing or for reading purposes at once. This might particularly be important due to noise reasons in testing applications, since the signals on the system bus 60 can influence the testing results. It is apparent that in those applications, a loading or (re-)loading of the channel memories 50AA, . . . , 50ZZ cannot be performed continuously or in parallel, e.g. for a processing or data output of the channel(s) 40AA, . . . , 40ZZ, and should be reduced to a minimum.
In operation, when the channel memories 50AA, . . . , 50ZZ are to be loaded with data, the main computer 20 receives the data to be loaded, e.g. from the data storage 30, and instructs the controller 70 to carry out the loading of the individual channel memories 50AA, . . . , 50ZZ. Accordingly, when a certain data is to be loaded form any one of the channel memories 50AA, . . . , 50Z, the main computer 20 instructs the controller 70 to carry out the reading from the respective channel memories 50AA, . . . , 50ZZ.
It has been found that certain applications, and in particular testing such as SCAN testing, e.g. on a digital IC test system, generally require large (`deep`) channel memories 50AA, . . . , 50ZZ, e.g. for sequentially storing SCAN test vectors. In the multi-channel architecture of FIG. 1 or 2, an own channel memory 50AA, . . . , 50ZZ for storing a program and/or respective data is provided for each one of the plurality of individual channels 40AA, . . . , 40ZZ. In the test-processor-per-pin-architecture in testing applications, an own channel memory 50AA, . . . , 50ZZ for storing a program and the respective test vectors must be provided for each testable pin of the DUT. However, since a high performance generally requires fast accessible and therefore expensive channel memories 50AA, . . . , 50ZZ, such as SRAMs or SDRAMs, the provided size of the channel memories 50AA, . . . , 50ZZ is typically not large enough, e.g. for an efficient SCAN testing.
There are several solutions known in the art to overcome the problem of an insufficient size of the channel memories 50AA, . . . , 50ZZ. A first possibility is to interrupt a data flow from the channel(s) 40AA, . . . , 40ZZ, e.g. during a SCAN test, when a respective one of the channel memories 50AA, . . . , 50ZZ becomes empty, and to reload data from the data storage 30 by means of the main computer 20 and the controller 70. However, this possibility generally fails for performance reasons, since the reloading of the channel memories 50AA, . . . , 50ZZ is relatively `slow` and thus requires a certain amount of time.
A second solution is to provide a few dedicated ones of the channel(s) 40AA, . . . , 40ZZ, e.g. as SCAN test channels, each with a deep channel memory 50AA, . . . , 50ZZ with respect to other ones of the channel(s) 40AA, . . . , 40ZZ. However, this solution suffers from a restricted flexibility of the channel(s) 40AA, . . . , 40ZZ, or a reduced accuracy, e.g. for test applications. In tester applications, the connection of the channels 40AA, . . . , 40ZZ as tester channels to the DUT is usually accomplished by means of an adaptor board. A new adaptor board must therefore be provided for each different DUT with a different test pinout. Further more, the integration of a switch matrix on the adaptor board between the tester connection and the DUT limits the accuracy and reliability.
A third approach is to add a dedicated memory board into the computer system 10. The main computer 20 loads all required data, e.g. SCAN test vectors required for a test, into this memory board before an application of the data, e.g. an execution of a test. During the application of the data, the channels 40AA, . . . , 40ZZ reload data from this memory board at a significant higher speed compared to solution one. The drawbacks are additional cost for the dedicated memory board and higher complexity for the reload mechanism.
A memory organisation in a central sequencer per test system is disclosed by Garry C. Gillette: "Tester takes on VLSI with 264-K vectors behind its pins", ELECTRONIC INTERNATIONAL, vol. 54, no.22, November 1981, New York, USA, pages 122-127, XP002056405. The central sequencer per test system sends, during a test cycle, 4 addresses to all 96 channels. The addresses go to a fast x and y memory, a slow z memory and a source select memory. A source select memory controls in each test cycle which memory will drive a pin, e.g. memory X or memory Y. The four addresses are common for all channels. During a scan test in the central sequencer machine, the memory of the neighbours n+1 or n-1 can be used for applying data to channel n. In that case, however, the used channel n+1 or n-1 cannot be used individually because of the common four address busses.
It is an object of the invention to provide an improved memory organization in computer systems with a multi-channel architecture. The object is solved by the features of the independent claims.
The invention is applied in a computer system having a multi-channel architecture wherein a plurality of individual channels having a respective channel memory and being connected by a bus. According to the invention, loading data, and preferably sequential data, into a channel memory of one of the plurality of individual channels is accomplished by:
(a) loading data into the channel memory to be loaded; PA1 (b) distributing further data which is to be loaded into the channel memory to be loaded into another channel memory of another one of the plurality of individual channels; and PA1 (c) reloading the data from the channel memory of the other one of the plurality of individual channels to the channel memory to be loaded via the bus.
The invention allows to provide a multi-channel architecture with a high parallelism and flexibility of the plurality of individual channels and the respective channel memories. The individual channels can be built up as identical modules comprising identical parts, so that not only the manufacturing and maintaining of the modules are improved, but also the flexibility of the channels is highly increased since each channel can be used for any application and is exchangeable and not custom built for only specific applications.
A different demand that will be made upon the individual channel memories, e.g. one of the individual channel memories is to be loaded with more data than the other channel memories, is balanced by applying the distributing and reloading of data according to the invention. The size of the individual channel memories can thus be limited and need not be the maximum size maybe only required for some specific applications. This again reduces the costs of the memories and thus of the entire system.
Further more, the reloading between the channel memories dramatically reduces the loading time in comparison to a direct loading from a central resource such as a central data storage of the computer system.
The invention can be preferably used for applying sequential data to the channels. This is particularly advantageous in testing applications such as SCAN testing, wherein generally a high amount of sequential data is to be applied to only a few channels whereas the other channels only require few data with respect to those channels. According to the invention, the already available memory of all the channels can be used for distributed storing of the data. This approach allows high performance testing with best flexibility and accuracy without additional cost.